Hardware/Firmware Configurations

About this page

The purpose of this page is to serve as a jumping-off point that describes the digital DAQ system in "functional mode slices". That is, taking a case-study approach starting with a desired operational mode and explaining how the hardware/firmware can be set up to do the desired function. Each item on this page links to a separate page with the specific answer.

format of answer pages

Each answer page linked to below should be in a standard format consisting of

• Statement describing exactly what the setup is supposed to do and why this is a useful setup.
• Picture showing what the inputs and outputs to the DAQ are.
• Explanation of which portions of the functionality are handled by the master trigger, the router trigger and the digitizer.
• Specific explanation of what data on each of the interconnecting SERDES links participates in this function.
• Specific explanation of which firmware blocks in each module are used to generate this function.
• Specific links to the formal documentation for further details.
• Explicit new drawings specific to the application that are explained with detailed text to show not only how it works but also how to set it up

List of answer pages

• How to regularly manufacture pedestal events in the data stream
• How trigger throttling works
• Generic answer template