How to regularly manufacture pedestal events in the data stream

THIS IS A TEST OF THE CONCEPT

Statement of desired functionality

A pedestal event is typically defined as one that captures data uncorrelated to detector activity but has timestamp information. This can be used to determine if the DC baseline is drifting over time such as from 60Hz noise, leakage currents, etc. To capture such information there has to be a way to make the digitizer's discriminator "fire" even though there's no edge to fire on, and a way to make this happen simultaneously across all digitizers but at a rate that is uncorrelated to the timestamp or beam frequency.

Picture showing relevant inputs and outputs

This functionality is available without any new connections to the DAQ. No new inputs or outputs are required.

Summary of solution

The digitizer firmware supports "external discriminator" features that allow non-waveform-related data capture. The external discriminator can be used in place of or as a signal ORed with the normal discriminator. In the OR mode a periodic external discriminator firing would create events in the digitizer that would measure pedestals. The trigger is capable of generating programmable regular timing signals in various ways that may be used with "external discriminator" mode to capture uncorrelated "pedestal" events. The trigger may also self-trigger when such signals are generated so that if the digitizers are running in the "TTCL" mode the uncorrelated events will all have a trigger accept message associated with them.

Breakdown of solution by module type

Master Trigger

To generate pedestal events the master must be capable of generating some periodic signal to the digitizers. This has two parts; signal generation and signal distribution.

    Signal Generation within the master trigger can be done most easily by using the Target Wheel Lookup RAMs.  There are three such RAMs in the master trigger, the Trigger RAM, the Veto RAM and the Sweep RAM.  Each dual-port RAM is 1024 x 1 in size, accessed through VME as a block of 64 sixteen-bit registers.  The second port of the dual-port RAM is read-only.  The address to the read-only port may come from various sources including an internal counter.  The internal counter has a decade rate divider to increment the address at 1Hz, 10Hz, 100Hz, etc. speeds.  By setting appropriate bits in the RAM a signal may be generated at regular intervals.  

Major firmware sections in use by module type

Other Devices

• Specific links to the formal documentation for further details.
• Explicit new drawings specific to the application that are explained with detailed text to show not only how it works but also how to set it up