PV List: Difference between revisions

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(Created page with " in terminal: caget = read PV value caput = set PV or command =========================== GOLBAL PV GLBL:DIG:<PV> -- for whole system VME$$:MDIG$$:<PV>...")
 
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  VME32:MTRG:XTHRESH
  VME32:MTRG:XTHRESH
  VME32:MTRG:YTHRESH
  VME32:MTRG:YTHRESH
VME32:RTR1:reg_MISC_STAT_RBV  | router lock state
VME32:RTR2:reg_MISC_STAT_RBV
= router lock state =
it is a 16bit hex number. for example, a good lock state is 17668 = 0x4504 = bx0100 0101 0000 0100
The bit is read like this: ( first bit is the most left bit )
bit-01 | Lock Error    |  0
bit-02 | All Lock      |  1
bit-03 | not use        |  0
bit-04 | not use        |  0
bit-05 | L init state 8 |  0
bit-06 | L init state 4 |  1
bit-07 | L init state 2 |  0
bit-08 | L init state 1 |  1
bit-09 | CPLD 8        |  0
bit-10 | CPLD 4        |  0
bit-11 | CPLD 2        |  0
bit-12 | CPLD 1        |  0
bit-13 | Fast str      |  0
bit-14 | R Lock        |  1
bit-15 | NIM in A      |  0
bit-16 | NIM in B      |  0

Revision as of 16:58, February 23, 2021

in terminal:

caget  =  read PV value
caput  =  set PV or command
=========================== GOLBAL PV
GLBL:DIG:<PV>            -- for whole system
VME$$:MDIG$$:<PV>        -- for whole digitizer
VME$$:MDIG$$:<PV>$$      -- for write indivual channel
VME$$:MDIG$$:<PV>$$_RBV  -- for read onlu
=====================+==========================+=======+========+=====+=====+
Items                | PV                       |  R/W  | Global | DIG |  CH |
=====================+==========================+=======+========+=====+=====+
Disc. Hits           | disc_count               |   R   |   X    |  X  |  O  |
Acc. Hits            | ahit_count               |   R   |   X    |  X  |  O  |
Acc. Evts            | accepted_event_count     |   R   |        |     |     | 
Drop. Evts           | dropped_event_count      |   R   |        |     |     |
Live TS              | CV_LiveTS                |   R   |        |     |     |
trigger mode         | trigger_mux_select       |  R/W  |        |     |     |
trig. pol.           | trigger_polarity         |  R/W  |   O    |  O  |  O  |
channel enable       | channel_enable           |  R/W  |   O    |  O  |  O  |
threshold            | led_threshold            |  R/W  |   O    |  O  |  O  |
                     | p1_window                |  R/W  |   O    |  O  |  O  |
                     | p2_window                |  R/W  |   O    |  O  |  X  |
                     | k_window                 |  R/W  |   O    |  O  |  O  |
                     | k0_window                |  R/W  |   O    |  O  |  O  |
                     | d_window                 |  R/W  |   O    |  O  |  O  |
                     | d2_window                |  R/W  |   O    |  O  |  O  |
                     | d3_window                |  R/W  |   O    |  O  |  O  |
                     | m_window                 |  R/W  |   O    |  O  |  O  |
                     | pileup_mode              |  R/W  |   O    |  O  |  O  |
Trace lenght  delay  | raw_data_length          |  R/W  |   O    |  O  |  O  |
Trace lenght         | raw_data_window          |  R/W  |   O    |  O  |  O  |
                     | CFD_fraction             |  R/W  |   O    |  O  |  O  |
Baseline   Delay     | delay                    |  R/W  |   O    |  O  |  X  |
Baseline channel     | baseline_start           |  R/W  |   O    |  O  |  O  |
Min overlap window   | win_comp_min             |  R/W  |   O    |  O  |  X  |
Max overlap window   | win_comp_max             |  R/W  |   O    |  O  |  X  |
Discr. Width         | disc_width               |  R/W  |   O    |  O  |  O  |
                     | peak_sensitivity         |  R/W  |   O    |  O  |  X  |
                     | tracking_speed           |  R/W  |   O    |  O  |  X  |
                     | preamp_reset_delay       |  R/W  |   O    |  O  |  O  |
                     | holdoff_time             |  R/W  |   O    |  O  |  X  |
                     | cfd_mode                 |  R/W  |   O    |  O  |  X  |
                     | veto_gate_width          |  R/W  |   O    |  X  |  X  |
enable preamp reset  | preamp_reset_delay_en    |  R/W  |   O    |  O  |  O  |
=====================+==========================+=======+========+=====+=====+
=========================== Other PV:
Online_CS_SaveData     | set Save Data register
Online_CS_StartStop    | set DAQ start stop
DAQC$_CV_SendRate
DAQC$_CV_NumSendBuffers
DAQC$_CV_BufferAvail

VME32:RTR$:TimestampB
VME32:MTRG:TIMESTAMP_B

VME32:RTR$:reg_MISC_STAT_RBV

VME32:MTRG:MAN/AUX.DESC
VME32:MTRG:SUM_X.DESC
VME32:MTRG:SUM_Y.DESC
VME32:MTRG:SUM_XY.DESC 

VME32:MTRG:RAW_TRIG_RATE_COUNTER_$_RBV

VME32:MTRG:XTHRESH
VME32:MTRG:YTHRESH

VME32:RTR1:reg_MISC_STAT_RBV   | router lock state
VME32:RTR2:reg_MISC_STAT_RBV 

router lock state

it is a 16bit hex number. for example, a good lock state is 17668 = 0x4504 = bx0100 0101 0000 0100

The bit is read like this: ( first bit is the most left bit )

bit-01 | Lock Error     |  0
bit-02 | All Lock       |  1
bit-03 | not use        |  0
bit-04 | not use        |  0
bit-05 | L init state 8 |  0
bit-06 | L init state 4 |  1
bit-07 | L init state 2 |  0
bit-08 | L init state 1 |  1
bit-09 | CPLD 8         |  0
bit-10 | CPLD 4         |  0
bit-11 | CPLD 2         |  0
bit-12 | CPLD 1         |  0
bit-13 | Fast str       |  0
bit-14 | R Lock         |  1
bit-15 | NIM in A       |  0
bit-16 | NIM in B       |  0