caget = read PV value caput = set PV or command
View the known PV list from the DAQ
in the DAQ, anywhere type
Get the full PV list from the DAQ
from John's email:
When you turn on the VME crate the MVME5500 processor performs its initial bootstrap and then goes out and loads a “command file” – this is basically like AUTOEXEC.BAT on a PC, a text file with a bunch of console commands. That “command file” will load some EPICS “database” files from a remote server. To edit the PVs we need to know what machine the MVME5500 uses as the remote boot host and where in that machine’s file structure the database file is located.
If you open up a terminal window to your trigger crate’s IOC console and enter the command ‘version’ it should print out some stuff about what version of VxWorks it is running and then say “Boot line:” followed by a path to a file. For instance the DGS trigger IOC says it’s boot line is
dgs1:/global/devel/boot/mvme5500/VxWorks <then a bunch of IPs and other junk, then finally> s=/global/devel/gretTop/9-22/dgsIoc/iocBoot/IocArray/vme32.cmd
It’s that last path after the “s=” that you’re interested in. That’s the location of the boot script for the processor. You want to look at that file to figure out where the EPICS database is stored for your system.
Inside that file you’ll find some lines that say dbLoadRecords(<path>,<args>); these are the actual database files. They should have an extension of either .template or .db. More than likely there are some ‘cd’ commands prior to these lines and the paths in the ‘dbLoadRecords’ lines will be relative to the place the last ‘cd’ took you. I would expect there to be a file RtrigRegisters.template.
At this point you know where the files are, but modifying them may require a recompile of your EPICS setup. So before going farther I will suggest that it is possible you have the PVs.
known PV list
=========================== GOLBAL PV GLBL:DIG:<PV> -- for whole system VME$$:MDIG$$:<PV> -- for whole digitizer VME$$:MDIG$$:<PV>$$ -- for write indivual channel VME$$:MDIG$$:<PV>$$_RBV -- for read onlu
=====================+==========================+=======+========+=====+=====+ Items | PV | R/W | Global | DIG | CH | =====================+==========================+=======+========+=====+=====+ Disc. Hits | disc_count | R | X | X | O | Acc. Hits | ahit_count | R | X | X | O | Acc. Evts | accepted_event_count | R | | | | Drop. Evts | dropped_event_count | R | | | | Live TS | CV_LiveTS | R | | | | trigger mode | trigger_mux_select | R/W | | | | trig. pol. | trigger_polarity | R/W | O | O | O | channel enable | channel_enable | R/W | O | O | O | threshold | led_threshold | R/W | O | O | O | | p1_window | R/W | O | O | O | | p2_window | R/W | O | O | X | | k_window | R/W | O | O | O | | k0_window | R/W | O | O | O | | d_window | R/W | O | O | O | | d2_window | R/W | O | O | O | | d3_window | R/W | O | O | O | | m_window | R/W | O | O | O | | pileup_mode | R/W | O | O | O | Trace lenght delay | raw_data_length | R/W | O | O | O | Trace lenght | raw_data_window | R/W | O | O | O | | CFD_fraction | R/W | O | O | O | Baseline Delay | delay | R/W | O | O | X | Baseline channel | baseline_start | R/W | O | O | O | Min overlap window | win_comp_min | R/W | O | O | X | Max overlap window | win_comp_max | R/W | O | O | X | Discr. Width | disc_width | R/W | O | O | O | | peak_sensitivity | R/W | O | O | X | | tracking_speed | R/W | O | O | X | | preamp_reset_delay | R/W | O | O | O | | holdoff_time | R/W | O | O | X | | cfd_mode | R/W | O | O | X | | veto_gate_width | R/W | O | X | X | enable preamp reset | preamp_reset_delay_en | R/W | O | O | O | =====================+==========================+=======+========+=====+=====+
=========================== Other PV: Online_CS_SaveData | set Save Data register Online_CS_StartStop | set DAQ start stop DAQC$_CV_SendRate DAQC$_CV_NumSendBuffers DAQC$_CV_BufferAvail VME32:RTR$:TimestampB VME32:MTRG:TIMESTAMP_B VME32:RTR$:reg_MISC_STAT_RBV VME32:MTRG:MAN/AUX.DESC VME32:MTRG:SUM_X.DESC VME32:MTRG:SUM_Y.DESC VME32:MTRG:SUM_XY.DESC VME32:MTRG:RAW_TRIG_RATE_COUNTER_$_RBV VME32:MTRG:XTHRESH VME32:MTRG:YTHRESH VME32:RTR1:reg_MISC_STAT_RBV | router lock state VME32:RTR2:reg_MISC_STAT_RBV VME32:RTR1:LOCK_COUNT_A_RBV | lock counter VME32:RTR1:LOCK_COUNT_B_RBV | lock counter VME32:RTR1:LOCK_COUNT_C_RBV | lock counter VME32:RTR1:CLEAR_DIAG_COUNTERS 1 | reset counter
router lock state
it is a 16bit hex number. for example, a good lock state is 17668 = 0x4504 = bx0100 0101 0000 0100
The bit is read like this: ( first bit is the most left bit )
bit-01 | Lock Error | 0 bit-02 | All Lock | 1 bit-03 | not use | 0 bit-04 | not use | 0 bit-05 | L init state 8 | 0 bit-06 | L init state 4 | 1 bit-07 | L init state 2 | 0 bit-08 | L init state 1 | 1 bit-09 | CPLD 8 | 0 bit-10 | CPLD 4 | 0 bit-11 | CPLD 2 | 0 bit-12 | CPLD 1 | 0 bit-13 | Fast str | 0 bit-14 | R Lock | 1 bit-15 | NIM in A | 0 bit-16 | NIM in B | 0
The db file
The IOC will load the database at boot up, the database is stored at /global/devel/gretTop/9-22/dgsIoc/db.
Here are the PV extracted from the dgsGlobals_HELIOS_VME01.db
=========================== Global PV VME01:GLBL:master_fifo_reset VME01:GLBL:ext_disc_src VME01:GLBL:user_package_data VME01:GLBL:win_comp_min VME01:GLBL:win_comp_max VME01:GLBL:channel_enable VME01:GLBL:pileup_mode VME01:GLBL:preamp_reset_delay_en VME01:GLBL:trigger_polarity VME01:GLBL:dropped_event_count_mode VME01:GLBL:enable_dec_pause VME01:GLBL:write_flags VME01:GLBL:decimation_factor VME01:GLBL:event_count_mode VME01:GLBL:ahit_count_mode VME01:GLBL:disc_count_mode VME01:GLBL:event_extention_mode VME01:GLBL:pileup_extention_mode VME01:GLBL:counter_reset VME01:GLBL:pileup_waveform_only_mode VME01:GLBL:led_threshold VME01:GLBL:preamp_reset_delay VME01:GLBL:CFD_fraction VME01:GLBL:raw_data_length VME01:GLBL:raw_data_window VME01:GLBL:d_window VME01:GLBL:k0_window VME01:GLBL:k_window VME01:GLBL:m_window VME01:GLBL:d3_window VME01:GLBL:d2_window VME01:GLBL:disc_width VME01:GLBL:baseline_start VME01:GLBL:p1_window VME01:GLBL:dac_channel_select VME01:GLBL:dac_attenuation VME01:GLBL:p2_window VME01:GLBL:DIAG_DISC_SEL VME01:GLBL:DIAG_WAVE_SEL VME01:GLBL:load_delays VME01:GLBL:phase_hunt VME01:GLBL:load_baseline VME01:GLBL:diag_mux_control VME01:GLBL:holdoff_time VME01:GLBL:auto_mode VME01:GLBL:peak_sensitivity VME01:GLBL:baseline_delay VME01:GLBL:delay VME01:GLBL:diag_input VME01:GLBL:diag_input_en VME01:GLBL:ext_disc_sel VME01:GLBL:ext_disc_ts_sel VME01:GLBL:rj45_discbit_mode VME01:GLBL:rj45_throttle_mode VME01:GLBL:output_mode VME01:GLBL:manual_data VME01:GLBL:veto_gate_width VME01:GLBL:master_logic_enable VME01:GLBL:diag_isync VME01:GLBL:counter_mode VME01:GLBL:master_counter_reset VME01:GLBL:BGO_discbit_select VME01:GLBL:veto_enable VME01:GLBL:cfd_mode VME01:GLBL:trigger_mux_select VME01:GLBL:tracking_speed VME01:GLBL:ts_err_count_ctrl VME01:GLBL:sd_rx_pwr VME01:GLBL:sd_local_loopback_en VME01:GLBL:sd_pem VME01:GLBL:sd_tx_pwr VME01:GLBL:sd_sync VME01:GLBL:sd_line_loopback_en VME01:GLBL:sd_sm_stringent_lock VME01:GLBL:sd_sm_lost_lock_flag VME01:GLBL:dc_balance _enable VME01:GLBL:config_main_fpga VME01:GLBL:config_diag_fpga VME01:GLBL:rst_main_fpga VME01:GLBL:rst_flash VME01:GLBL:config_override VME01:GLBL:clk_select VME01:GLBL:flash_mode VME01:GLBL:vme_sandboxA VME01:GLBL:vme_sandboxB VME01:GLBL:vme_sandboxC VME01:GLBL:vme_sandboxD
Gloabl PV found : 87
=========================== MDIG PV VME01:MDIG1:ext_disc_src VME01:MDIG1:channel_enable VME01:MDIG1:pileup_mode VME01:MDIG1:preamp_reset_delay_en VME01:MDIG1:trigger_polarity VME01:MDIG1:dropped_event_count_mode VME01:MDIG1:enable_dec_pause VME01:MDIG1:write_flags VME01:MDIG1:decimation_factor VME01:MDIG1:decimation_factor VME01:MDIG1:event_count_mode VME01:MDIG1:ahit_count_mode VME01:MDIG1:disc_count_mode VME01:MDIG1:event_extention_mode VME01:MDIG1:pileup_extention_mode VME01:MDIG1:counter_reset VME01:MDIG1:pileup_waveform_only_mode VME01:MDIG1:led_threshold VME01:MDIG1:preamp_reset_delay VME01:MDIG1:CFD_fraction VME01:MDIG1:raw_data_length VME01:MDIG1:raw_data_window VME01:MDIG1:d_window VME01:MDIG1:k0_window VME01:MDIG1:k_window VME01:MDIG1:m_window VME01:MDIG1:d3_window VME01:MDIG1:d2_window VME01:MDIG1:disc_width VME01:MDIG1:baseline_start VME01:MDIG1:p1_window VME01:MDIG1:ext_disc_sel VME01:MDIG1:clk_select
MDIG PV found : 33