ANL Digitizer Firmware for Advanced Users: Difference between revisions

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== A Short Introduction to Hardware ==
== [[A Short Introduction to Data Acquisition Hardware]] ==
To fully understand how the firmware works the hardware environment must be explained.  
To fully understand how the firmware works the hardware environment must be explained. This section briefly introduces the concept of '''Master and Slave digitizers''', '''Clocking and Timestamps''', and '''Connecting the Trigger to External Systems'''.


The digitizer module contains two FPGAs, one for VME interface and firmware maintenance purposes, and the other for ADC data processing, as shown in Figure 1.
The digitizer module contains two FPGAs, one for VME interface and firmware maintenance purposes, and the other for ADC data processing, as shown in Figure 1.
Line 14: Line 14:
*If the physical setup exceeds these bounds, non-linearity will distort waveform shapes.
*If the physical setup exceeds these bounds, non-linearity will distort waveform shapes.


=== "Master" and "Slave" Digitizers ===
== [[General Design of the Firmware]] ==
The digitizer modules may be used in pairs where one digitizer is labeled the “master” and the other is labeled the “slave”.  In this configuration the two digitizers have ''different versions of firmware''.  The “master” digitizer alone connects to the trigger system.  A ribbon cable connects the “master” digitizer to the “slave” digitizer.  The “slave” digitizer channels are normally configured to use signals from the “master” digitizer as part of the logic determining if discriminators within the “slave” channels will fire or not, or whether events within the “slave” are marked for readout or not.
This section introduces mid-level descriptions for the topics of '''''Event Data Nomenclature''''', '''''Discriminator Modes''''', '''''Pileup Rejection''''', and '''''Diagnostic Counters'''''.


=== Clocking and Timestamps ===
The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels.  Pileup detection & rejection is performed locally within the digitizer.  Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit.  
The ADC chips run at a frequency of 100MHz (100 MSamp/sec).  The device may run from its own internal oscillator or may receive a clock from an external trigger system and synchronize to that clock.  A clock distribution from the trigger allows many digitizer modules to run synchronous to each other.


The digitizer module uses a 48-bit timestamp counter run from the 100MHz clock. When connected to the trigger system, the trigger may issue a command to synchronously reset the timestamp in all digitizers. Events read out of the digitizer are tagged with a timestamp for sorting and analysis.
Each '''channel pipeline''' consists of a series of memory buffers used for delay. When sampling occurs, the timestamp value is saved.  The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges. Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth ([[IOC Code Design]]).


=== Connection to External Trigger System ===
All sampled values and sums are formatted into an '''event header''' that is followed by a programmable number of waveform samples.  The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing.
Digitizer modules may connect to a trigger system for synchronization and event selection purposes.  A separate cable plant connects digitizer modules to trigger modules; on the digitizer end the cable uses the same RJ45 connector as Ethernet, but the signal levels and usage '''''are not Ethernet'''''.  '''Do not connect the digitizer to an Ethernet port, this will damage the digitizer module'''.


The digitizer can run standalone without being connected to a trigger system.  In this configuration every digitizer board has independent and unsynchronized clocks. Timestamps for event sorting are not useful across multiple modules as there is no synchronism, but within one board timestamps are still sensible.
Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires.  Programmable '''delay buffers''' positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. These sums may then be used by ''open source user-maintained software'' (see the gitlab link in [[analysis codes]] for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header.


''See '''MyRIAD_USER_Manaual''' or '''MyRIAD_Abridged_User_Notes''' in [[Original Content prior to the ''Gammasphere Upgrade Project'']] for detailed information on External Trigger systems''.
Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions.  Specific triggering modes appropriate to the different detector systems at ANL have been developed.  


== General Design of the Firmware ==
== [[Digitizer Channel Design Overview]] ==
The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels.  Pileup detection & rejection is performed locally within the digitizer.  Selective readout of events is achieved using an external trigger system.  Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit.  A down-sampling mode allows readout of averaged samples where each waveform sample in the readout may be the average of 2n ADC samples, from 2 to 128 (n = 0, 1, 2,…, 6, 7).  Increased event rates are obtained by limiting the amount of waveform data read out per event.
This section covers mid-level descriptions of '''''Digitizer Channel Design''''', '''''Channel Interactions''''', and '''''Pipeline Structure'''''


Each channel pipeline consists of a series of memory buffers used for delay.  Discriminator logic recognizes edges within the input signal and causes data values to be sampled.  When sampling occurs, the timestamp value is saved.  The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges.  The discriminator implements a programmable hold-off time to ensure that the discriminator fires only once per edge.  A discriminator firing captures timing and data sums simultaneously.  This data is buffered so that discriminator re-arms very quickly.  Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth ([[IOC Code Design]]).  No information reduction occurs in pileup conditions due to the fast discriminator recovery time.
In the middle of the pipeline multiple delay buffers with accumulators provide running sums of the data spanning programmable ranges of time.


All sampled values and sums are formatted into an '''event header''' that is followed by a programmable number of waveform samples. The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing.  Flag bits provide useful diagnostics.  The waveform data contains the raw ADC samples of the event, plus serialized timing mark bits that indicate when specific actions (discriminator, peak, timeouts, etc.) occurred and a 2nd bit that indicates whether samples are down-sampled (rescaled average of 2**n samples) or full-speed.
[[File:Dig pic 44.png|center|Figure 2: 10 channel data flow diagram.]]


Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires.  Programmable '''delay buffers''' positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. When the discriminator fires these sums are saved and reported in the header.  These sums may then be used by ''open source user-maintained software'' (see the gitlab link in [[analysis codes]] for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header.  This method is arithmetically identical to the traditional “trapezoid” method but is optimized for high rates of discriminator operation.
=== Pipeline Structure ===
The pipeline structure found in every channel is shown as Figure 3.  The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image.  When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.
*Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.


Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers.  The reverse logic is also supported, in which only piled-up events are available for readout.  The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions.  Specific triggering modes appropriate to the different detector systems at ANL have been developed.  
[[File:Dic pic 40.png|center|Figure 3: Pipeline structure of channel showing progression of waveform with time.]]


The channel pipelines have two basic modes of operation, Leading-Edge Discriminator and Constant-Fraction Discriminator. Data in both modes reads out as a packet consisting of ''header'' followed by ''waveform''.


==Readout Data Format==
VME data readout is always 32-bit words. A ''header type'' value in the ''header'' indicates which mode the channel was in when the data was taken. A ''header length'' field indicates how many 32-bit words are in the ''header'', and a separate ''packet length'' field states the total length of ''header'' plus ''waveform''. 


=== Data Header ===
The header format for the ANL digitizer was updated with ''header types'' 7 & 8 for the August 2021 release. Header type 7 corresponds to LED mode, and header type 8 corresponds to CFD mode of operation. All data read from the digitizer is 32 bits wide, and the header is 14 words long.


''Go back to [[Digital Gammasphere and the SBX Upgrade]]''
''Go Back to [[Advanced User Guides]]''
 
''Go back to [[Digital Gammasphere Upgrade Project]]''

Latest revision as of 19:51, October 18, 2021

A Short Introduction to Data Acquisition Hardware

To fully understand how the firmware works the hardware environment must be explained. This section briefly introduces the concept of Master and Slave digitizers, Clocking and Timestamps, and Connecting the Trigger to External Systems.

The digitizer module contains two FPGAs, one for VME interface and firmware maintenance purposes, and the other for ADC data processing, as shown in Figure 1.

Figure 1: Overall block diagram of digitizer module.

Input Signals

Signals at the digitizer input are differential. The input range is limited. While the ADC chip the module uses nominally has a +/-2V differential input (that is, + to – may range from -2V to +2V) the input buffer circuitry does not have sufficient power supply voltage headroom to support this full range. The device works very well for signals that range between -1.5V to +1.5V differential, but signal compression occurs beyond those limits. Linearity studies performed at ANL show that the device is almost perfectly linear for an input range of -1.2V to +1.2V but small deviations from linearity are discernable from 1.2V to 1.5V with marked deviations occurring past 1.5V.

In terms of ADC counts, since the ADC chip is designed to span 16,384 codes over 4 volts, this means that the conversion is 4096 counts per volt. Thus

  • For absolute best linearity, limit the DC offset and signal range to no more than ±(1.2 * 4096), or ±4916 counts, from the nominal 0V level of 8192 counts (3276 to 13108).
  • For all but the most stringent requirements, a more relaxed range of ±(1.5 * 4096), or ±6144 counts, will suffice (2048 to 14336).
  • If the physical setup exceeds these bounds, non-linearity will distort waveform shapes.

General Design of the Firmware

This section introduces mid-level descriptions for the topics of Event Data Nomenclature, Discriminator Modes, Pileup Rejection, and Diagnostic Counters.

The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit.

Each channel pipeline consists of a series of memory buffers used for delay. When sampling occurs, the timestamp value is saved. The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges. Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth (IOC Code Design).

All sampled values and sums are formatted into an event header that is followed by a programmable number of waveform samples. The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing.

Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires. Programmable delay buffers positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. These sums may then be used by open source user-maintained software (see the gitlab link in analysis codes for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header.

Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.

Digitizer Channel Design Overview

This section covers mid-level descriptions of Digitizer Channel Design, Channel Interactions, and Pipeline Structure

In the middle of the pipeline multiple delay buffers with accumulators provide running sums of the data spanning programmable ranges of time.

Figure 2: 10 channel data flow diagram.

Pipeline Structure

The pipeline structure found in every channel is shown as Figure 3. The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image. When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.

  • Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.
Figure 3: Pipeline structure of channel showing progression of waveform with time.

The channel pipelines have two basic modes of operation, Leading-Edge Discriminator and Constant-Fraction Discriminator. Data in both modes reads out as a packet consisting of header followed by waveform.

Readout Data Format

VME data readout is always 32-bit words. A header type value in the header indicates which mode the channel was in when the data was taken. A header length field indicates how many 32-bit words are in the header, and a separate packet length field states the total length of header plus waveform.

Data Header

The header format for the ANL digitizer was updated with header types 7 & 8 for the August 2021 release. Header type 7 corresponds to LED mode, and header type 8 corresponds to CFD mode of operation. All data read from the digitizer is 32 bits wide, and the header is 14 words long.

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