DAC output

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Digitizer DAC output

The digitizer has a fast, but low resolution (10 bit) DAC. The DAC output is driven psuedo-differentially out two connectors on the front panel. One output is the plus side, one the minus side. The DAC is noisy and is not suitable for seeing fine detail. There is a ton of 100MHz clock pickup from the board's oscillator. The DAC is only usable if you bandwidth-limit the scope probe to 20MHz. For most applications you also want to average traces if at all possible.

DAC functionality in latest version of firmware

The 20180607 firmware release for the digitizer (SVN index #4830) was compiled with the command-line options of "SLAVE_MODE=0, DIAG_MUX_SIZE=0, INCLUDE_DSP_ILA=0, INCLUDE_LVME_ILA=0". The DIAG_MUX_SIZE=0 option disables the DAC by setting the data sent to the DAC to be a constant zero; the compiler then optimizes out all possible DAC choices. The link to this "standard release" version is

https://svn.inside.anl.gov/repos/dgs/Firmware_Tags/Digitizer/MAIN_FPGA_TAGS/20180607/MAIN_FPGA/BuildBranches/DGS/Work/MSTR_digitizer.bin


Optional firmware choices

A secondary compilation of the 20180607 firmware release with DIAG_MUX_SIZE=2 is also available. This variant is found at

https://svn.inside.anl.gov/repos/dgs/Firmware_Tags/Digitizer/MAIN_FPGA_TAGS/20180607/MAIN_FPGA/BuildBranches/DGS/Work/MSTR_digitizer_full_dac.bin


  • A build with DIAG_MUX_SIZE=2 provides a two-level mux that allows you to get the waveform from a couple different points in the delay chain, from any channel, with variable gain.
  • The reg_dac register at address 0x400 provides some of the selection logic.
    • Bits 3:0 select which channel the dac data comes from.
    • Bits 7:4 control shift logic to adjust the data sent to the DAC. The DAC itself is only 8 bits but the data from the channel logic is 16 bits wide. So the value in bits 7:4 of the register selects which 8-bit data range (bits 15:8, 14:7, ..., 8:1 or 7:0 go to the DAC. The value written to the field of the register is the bit index of the LSB going to the DAC (e.g. writing 4 gives you bits 11:4).


  • A second level of selection is within the channel itself. The DIAG_MUX_CTL register at address 0x410 lets you select one of four choices for the data sent to the DAC mux described above from the channel.
    • 0 sends the raw ADC data samples from the beginning of the pipeline, at the point after the P2 delay buffer but before the post-rise M buffer.
    • 1 sends a single bit at bit position 8 in the 16-bit data. The single bit is the BASELINE_IS_TRACKING flag, used to monitor baseline tracker logic activity.
    • 2 sends the raw ADC data samples from a spot in the middle of the pipeline, at the point after the 'k' buffer but before the 'd' buffer.
    • 3 sends the 14-bit fully filtered baseline value from the baseline tracking logic.

EPICS hooks to DAC features

  • The EPICS PV VMExx:MDIGx:dac_channel_select connects to bits 3:0 of the reg_dac register and thus provides dac channel selection.
  • The EPICS PV VMExx:MDIGx:dac_attenuation connects to bits 7:4 of the reg_dac register and thus provides dac attenuation factor control.
  • The EPICS PV VMExx:MDIGx:diag_mux_control connects to bits 1:0 of the DIAG_MUX_CTL register as described above. The options listed in the EPICS database are out of date and misleading.
    • The EPICS control value "rawADC" is the value 0, so is essentially correct.
    • The EPICS control value "RunSumM" is the value 1, so is misleading.
    • The EPICS control value "FiltSimDisc" is the value 2, so is misleading.
    • The EPICS control value "NULL" is value 3, so is misleading.