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This special page shows all uploaded files.
| Date | Name | Thumbnail | Size | User | Description | Versions |
|---|---|---|---|---|---|---|
| 18:35, July 23, 2013 | Gammaware1.JPG (file) |  |
310 KB | Jta | 1 | |
| 18:49, July 23, 2013 | Gammaware3.JPG (file) |  |
67 KB | Jta | 1 | |
| 18:53, July 23, 2013 | Gammaware2.JPG (file) |  |
55 KB | Jta | 1 | |
| 19:00, October 16, 2017 | GeTempMon.png (file) |  |
41 KB | Jta | 1 | |
| 20:52, October 30, 2017 | DGSCommander main.png (file) |  |
23 KB | Jta | 1 | |
| 20:52, October 30, 2017 | VME IOC Summary.png (file) |  |
19 KB | Jta | 1 | |
| 21:03, April 27, 2018 | MyRIAD User Manaual.pdf (file) |  |
918 KB | Jta | Full user manual for the MyRIAD | 1 |
| 21:04, April 27, 2018 | MyRIAD Abridged User Notes.pdf (file) | |
340 KB | Jta | Shorter notes on just I/O connections for impatient readers. | 1 |
| 18:54, May 1, 2018 | DGS trigger system firmware user guide.pdf (file) | |
488 KB | Jta | General introduction to the trigger system | 1 |
| 18:56, May 1, 2018 | MYRIAD Module Specification.pdf (file) | |
247 KB | Jta | Overall description of the MyRIAD. | 1 |
| 18:58, May 1, 2018 | ANL Firmware for LBL Digitizer.pdf (file) | |
1.25 MB | Jta | Detail documentation for the digitizer firmware used at ANL. | 1 |
| 19:03, May 1, 2018 | 20160418 trig command link.pdf (file) | |
860 KB | Jta | document describing trigger-to-digitizer communication. | 1 |
| 19:04, May 1, 2018 | CPLD sum logic.pdf (file) | |
240 KB | Jta | 1 | |
| 19:07, May 1, 2018 | Interfacing Digital Gammasphere with other detectors and systems.pdf (file) | |
813 KB | Jta | 1 | |
| 19:12, May 1, 2018 | TripletPulseNotesTake2.pdf (file) | |
357 KB | Jta | An example of using the digitizer tester to explore digitizer operation with different readout & integration settings | 1 |
| 19:18, May 1, 2018 | AsynDebugDriverDOCS.pdf (file) | |
268 KB | Jta | 1 | |
| 19:19, May 1, 2018 | DebuggingEPICSChannelAccess.pdf (file) | |
350 KB | Jta | 1 | |
| 19:20, May 1, 2018 | DigitalGammasphereSW.pdf (file) | |
827 KB | Jta | 1 | |
| 19:23, May 1, 2018 | PythonEPICS.pdf (file) | |
84 KB | Jta | 1 | |
| 23:55, December 12, 2018 | DGS crate mapping.xlsx (file) |  |
32 KB | Jta | Crate map spreadsheet for DGS. | 1 |
| 03:24, April 18, 2019 | DGSImageMap.png (file) |  |
78 KB | Jta | 1 | |
| 20:24, April 20, 2019 | DigitizerIOC.PNG (file) |  |
19 KB | Jta | 1 | |
| 16:57, September 11, 2019 | ClockHierarchy.png (file) |  |
26 KB | Jta | updated with a couple typos fixed. | 2 |
| 17:05, September 11, 2019 | FullSystem.png (file) |  |
33 KB | Jta | full system picture. | 1 |
| 20:18, September 11, 2019 | Ttcl cutout.PNG (file) |  |
117 KB | Jta | part of the manual no one has ever read. | 1 |
| 20:47, September 11, 2019 | RemoteTriggerQueuing.png (file) |  |
39 KB | Jta | 1 | |
| 21:08, September 11, 2019 | RemoteTrigAlgorithm.PNG (file) |  |
22 KB | Jta | 1 | |
| 21:21, September 11, 2019 | MyriadTrigAlgorithm.PNG (file) |  |
37 KB | Jta | 1 | |
| 19:29, May 28, 2020 | Header colorkey.png (file) |  |
7 KB | Jta | color keying for digitizer/trigger data format pictures. | 1 |
| 14:21, June 26, 2020 | Screensmap.JPG (file) |  |
96 KB | Eye | 1 | |
| 01:56, July 3, 2020 | Screenshot-17.png (file) |  |
67 KB | Jta | PDU #1 screen shot | 1 |
| 01:56, July 3, 2020 | Screenshot-18.png (file) |  |
67 KB | Jta | pdu control screen 2 | 1 |
| 16:40, July 8, 2020 | Generation of C and VHDL from spreadsheet.docx (file) | |
274 KB | EYE | 1 | |
| 20:03, July 31, 2020 | Python Materials.zip (file) | |
1.18 MB | EYE | 1 | |
| 20:25, September 16, 2021 | IOC State Diagram for inLoop.jpg (file) |  |
255 KB | Copp | 1 | |
| 20:35, September 16, 2021 | Digitizer FIFO and Throttle.jpg (file) |  |
330 KB | Copp | 1 | |
| 20:49, September 16, 2021 | Trigger Throttle.jpg (file) |  |
128 KB | Copp | 1 | |
| 21:12, September 16, 2021 | InLoop Header.jpg (file) |  |
740 KB | Copp | 1 | |
| 21:14, September 16, 2021 | Trigger Header Format.jpg (file) |  |
282 KB | Copp | 1 | |
| 15:44, September 20, 2021 | Dig pic 31.png (file) |  |
23 KB | Jta | Delay buffers per channel have differing widths for implementation of delays without counters | 1 |
| 15:45, September 20, 2021 | Dig pic 32.png (file) |  |
47 KB | Jta | Timing of CHAIN_INVALID and sequenced initialization thereafter | 1 |
| 15:46, September 20, 2021 | Dig pic 33.png (file) |  |
44 KB | Jta | pileup timing | 1 |
| 15:47, September 20, 2021 | Dic pic 34.png (file) |  |
49 KB | Jta | timing mark formation, LED mode | 1 |
| 15:48, September 20, 2021 | Dig pic 35.png (file) |  |
47 KB | Jta | pileup timing in CFD mode | 1 |
| 15:49, September 20, 2021 | Dig pic 36.png (file) |  |
41 KB | Jta | other timing delays | 1 |
| 15:49, September 20, 2021 | Dig pic 37.png (file) |  |
61 KB | Jta | header formation and pehq | 1 |
| 15:50, September 20, 2021 | Dig pic 38.png (file) |  |
38 KB | Jta | led mode waveform overlay | 1 |
| 15:51, September 20, 2021 | Dig pic 39.png (file) |  |
44 KB | Jta | cfd discriminator pre-arming | 1 |
| 15:51, September 20, 2021 | Dic pic 40.png (file) |  |
37 KB | Jta | 1 | |
| 15:52, September 20, 2021 | Dig pic 41.png (file) |  |
22 KB | Jta | 1 |
