Beginner Guide to Digitizer Firmware: Difference between revisions
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Data from the ADCs of the digitizer is signed 14-bit values that arrive at 100MHz (10ns period). Each digitizer module implements ten channels that implement independent input and energy integration blocks. The purpose of the input and energy integration firmware block, implemented as a pipeline, is to receive the data, internally trigger on edges of signals and calculate the energy of the input signal. Following each energy integrator is a pending event queue and event acceptance logic block that places accepted events into channel-specific FIFO buffers. At the back end, a channel readout machine collects all data from the channels and stuffs accepted events into a large external readout FIFO, accessible over the VME backplane. | Data from the ADCs of the digitizer is signed 14-bit values that arrive at 100MHz (10ns period). Each digitizer module implements ten channels that implement independent input and energy integration blocks. The purpose of the input and energy integration firmware block, implemented as a pipeline, is to receive the data, internally trigger on edges of signals and calculate the energy of the input signal. Following each energy integrator is a pending event queue and event acceptance logic block that places accepted events into channel-specific FIFO buffers. At the back end, a channel readout machine collects all data from the channels and stuffs accepted events into a large external readout FIFO, accessible over the VME backplane. | ||
Further details can be found in ''Advanced Guide to Digitizer Firmware''. | Further details can be found in ''[[Advanced Guide to Digitizer Firmware]]''. | ||
Two versions of firmware have been developed, a Master build and a Slave build. These operate identically in virtually all ways save that the Master build directly interfaces to the trigger system and the Slave build receives its clock and control signals from the trigger over a front panel cable driven by the Master. | Two versions of firmware have been developed, a Master build and a Slave build. These operate identically in virtually all ways save that the Master build directly interfaces to the trigger system and the Slave build receives its clock and control signals from the trigger over a front panel cable driven by the Master. | ||
Latest revision as of 19:41, September 20, 2021
Intro
This is a brief introduction guide to the digitizer firmware (September 2021).
The digitizer module design and the original GRETINA firmware developed for it are products of Lawrence Berkeley National Laboratory (LBNL). The trigger module and its firmware are products of Argonne National Laboratory (ANL). We at Argonne thank our LBNL collaborators for sharing the source code and schematics of the digitizer module, both of which were invaluable references in this totally new firmware development.
Overview of Digitizer
Data from the ADCs of the digitizer is signed 14-bit values that arrive at 100MHz (10ns period). Each digitizer module implements ten channels that implement independent input and energy integration blocks. The purpose of the input and energy integration firmware block, implemented as a pipeline, is to receive the data, internally trigger on edges of signals and calculate the energy of the input signal. Following each energy integrator is a pending event queue and event acceptance logic block that places accepted events into channel-specific FIFO buffers. At the back end, a channel readout machine collects all data from the channels and stuffs accepted events into a large external readout FIFO, accessible over the VME backplane.
Further details can be found in Advanced Guide to Digitizer Firmware.
Two versions of firmware have been developed, a Master build and a Slave build. These operate identically in virtually all ways save that the Master build directly interfaces to the trigger system and the Slave build receives its clock and control signals from the trigger over a front panel cable driven by the Master.