Updating Firmware in Modules

Some more notes about flashing digitizers or triggers:

1. Log into dgs account on dgs1
2. Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS
3. copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware
4. cd /home/dgs/tmadden/swWork/workspace/epicsClient/src
5. issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl
   
6. copy and paste below

epics.epics_init();
var fn0=new String("/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt");
var fn1=new String("/home/dgs/tmadden/retfile.bin");
epics.connectPVs(fn0);
var digware=new String("/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin");
var slvware=new String("/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin");
var mastware=new String("/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin");
var routware=new String("/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin");

-NOTE: Need to define add current name of master, slave digitizer bin files and trigger & router bin file names
-NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.
-NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.

If you get this far, you are now ready to flash the individual digitizers

• To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);
  • This line sends the firmware file defined in digware to the board.
  • The args of the function are defined as:   
    • Firmwarename, ret file name, Crate num, Board num, erase, program, verify
  • IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.
• To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient.
• To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs.
• For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too.
  

For master trigger
epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);

For routers
epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);
epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);
epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);

add these for FMA

epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);
epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);

DGS Digitizers

master digitzers
epics.sendFpga(digware, fn1, 1, 0, 1,1,0);
epics.sendFpga(digware, fn1, 1, 2, 1,1,0);
epics.sendFpga(digware, fn1, 2, 0, 1,1,0);
epics.sendFpga(digware, fn1, 2, 2, 1,1,0);
epics.sendFpga(digware, fn1, 3, 0, 1,1,0);
epics.sendFpga(digware, fn1, 3, 2, 1,1,0);
epics.sendFpga(digware, fn1, 4, 0, 1,1,0);
epics.sendFpga(digware, fn1, 4, 2, 1,1,0);
epics.sendFpga(digware, fn1, 5, 0, 1,1,0);
epics.sendFpga(digware, fn1, 5, 2, 1,1,0);
epics.sendFpga(digware, fn1, 6, 0, 1,1,0);
epics.sendFpga(digware, fn1, 6, 2, 1,1,0);
epics.sendFpga(digware, fn1, 7, 0, 1,1,0);
epics.sendFpga(digware, fn1, 7, 2, 1,1,0);
epics.sendFpga(digware, fn1, 8, 0, 1,1,0);
epics.sendFpga(digware, fn1, 8, 2, 1,1,0);
epics.sendFpga(digware, fn1, 9, 0, 1,1,0);
epics.sendFpga(digware, fn1, 9, 2, 1,1,0);
epics.sendFpga(digware, fn1, 10, 0, 1,1,0);
epics.sendFpga(digware, fn1, 10, 2, 1,1,0);
epics.sendFpga(digware, fn1, 11, 0, 1,1,0);
epics.sendFpga(digware, fn1, 11, 2, 1,1,0);

slave digitzers

epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);
epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);
epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);

For Non-Slave Configuration (FMA):

epics.sendFpga(digware, fn1, 1, 0, 1,1,1);
epics.sendFpga(digware, fn1, 1, 1, 1,1,1);
epics.sendFpga(digware, fn1, 1, 2, 1,1,1);
epics.sendFpga(digware, fn1, 1, 3, 1,1,1);
epics.sendFpga(digware, fn1, 2, 0, 1,1,1);
epics.sendFpga(digware, fn1, 2, 1, 1,1,1);
epics.sendFpga(digware, fn1, 2, 2, 1,1,1);
epics.sendFpga(digware, fn1, 2, 3, 1,1,1);
epics.sendFpga(digware, fn1, 3, 0, 1,1,1);
epics.sendFpga(digware, fn1, 3, 1, 1,1,1);
epics.sendFpga(digware, fn1, 3, 2, 1,1,1);
epics.sendFpga(digware, fn1, 3, 3, 1,1,1);
epics.sendFpga(digware, fn1, 4, 0, 1,1,1);
epics.sendFpga(digware, fn1, 4, 1, 1,1,1);
epics.sendFpga(digware, fn1, 4, 2, 1,1,1);
epics.sendFpga(digware, fn1, 4, 3, 1,1,1);
epics.sendFpga(digware, fn1, 5, 0, 1,1,1);
epics.sendFpga(digware, fn1, 5, 1, 1,1,1);
epics.sendFpga(digware, fn1, 5, 2, 1,1,1);
epics.sendFpga(digware, fn1, 5, 3, 1,1,1);
epics.sendFpga(digware, fn1, 6, 0, 1,1,1);
epics.sendFpga(digware, fn1, 6, 1, 1,1,1);
epics.sendFpga(digware, fn1, 6, 2, 1,1,1);
epics.sendFpga(digware, fn1, 6, 3, 1,1,1);
epics.sendFpga(digware, fn1, 7, 0, 1,1,1);
epics.sendFpga(digware, fn1, 7, 1, 1,1,1);
epics.sendFpga(digware, fn1, 7, 2, 1,1,1);
epics.sendFpga(digware, fn1, 7, 3, 1,1,1);
epics.sendFpga(digware, fn1, 8, 0, 1,1,1);
epics.sendFpga(digware, fn1, 8, 1, 1,1,1);
epics.sendFpga(digware, fn1, 8, 2, 1,1,1);
epics.sendFpga(digware, fn1, 8, 3, 1,1,1);
epics.sendFpga(digware, fn1, 9, 0, 1,1,1);
epics.sendFpga(digware, fn1, 9, 1, 1,1,1);
epics.sendFpga(digware, fn1, 9, 2, 1,1,1);
epics.sendFpga(digware, fn1, 9, 3, 1,1,1);