ANL Digitizer Firmware for Advanced Users - Revision history

Copp at 19:51, October 18, 2021

2021-10-18T19:51:14Z

← Older revision		Revision as of 19:51, October 18, 2021
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	VME data readout is always 32-bit words. A ''header type'' value in the ''header'' indicates which mode the channel was in when the data was taken. A ''header length'' field indicates how many 32-bit words are in the ''header'', and a separate ''packet length'' field states the total length of ''header'' plus ''waveform''.		VME data readout is always 32-bit words. A ''header type'' value in the ''header'' indicates which mode the channel was in when the data was taken. A ''header length'' field indicates how many 32-bit words are in the ''header'', and a separate ''packet length'' field states the total length of ''header'' plus ''waveform''.

	=== [[Data Header]] ===		=== Data Header ===
	The header format for the ANL digitizer was updated with ''header types'' 7 & 8 for the August 2021 release. Header type 7 corresponds to LED mode, and header type 8 corresponds to CFD mode of operation. All data read from the digitizer is 32 bits wide, and the header is 14 words long.		The header format for the ANL digitizer was updated with ''header types'' 7 & 8 for the August 2021 release. Header type 7 corresponds to LED mode, and header type 8 corresponds to CFD mode of operation. All data read from the digitizer is 32 bits wide, and the header is 14 words long.

Copp at 19:46, October 18, 2021

2021-10-18T19:46:34Z

← Older revision		Revision as of 19:46, October 18, 2021
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	[[File:Dic pic 40.png\|center\|Figure 3: Pipeline structure of channel showing progression of waveform with time.]]		[[File:Dic pic 40.png\|center\|Figure 3: Pipeline structure of channel showing progression of waveform with time.]]

			The channel pipelines have two basic modes of operation, Leading-Edge Discriminator and Constant-Fraction Discriminator. Data in both modes reads out as a packet consisting of ''header'' followed by ''waveform''.

			==Readout Data Format==
			VME data readout is always 32-bit words. A ''header type'' value in the ''header'' indicates which mode the channel was in when the data was taken. A ''header length'' field indicates how many 32-bit words are in the ''header'', and a separate ''packet length'' field states the total length of ''header'' plus ''waveform''.

			=== [[Data Header]] ===
			The header format for the ANL digitizer was updated with ''header types'' 7 & 8 for the August 2021 release. Header type 7 corresponds to LED mode, and header type 8 corresponds to CFD mode of operation. All data read from the digitizer is 32 bits wide, and the header is 14 words long.

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Copp: /* Pipeline Structure */

2021-10-18T19:11:29Z

Pipeline Structure

← Older revision		Revision as of 19:11, October 18, 2021
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	[[File:Dig pic 44.png\|center\|Figure 2: 10 channel data flow diagram.]]		[[File:Dig pic 44.png\|center\|Figure 2: 10 channel data flow diagram.]]

	=== [[Pipeline Structure]] ===		=== Pipeline Structure ===
	The pipeline structure found in every channel is shown as Figure 3. The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image. When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.		The pipeline structure found in every channel is shown as Figure 3. The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image. When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.
	*Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.		*Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.

Copp: /* Digitizer Channel Design Overview */

2021-10-18T19:10:36Z

Digitizer Channel Design Overview

← Older revision		Revision as of 19:10, October 18, 2021
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	[[File:Dig pic 44.png\|center\|Figure 2: 10 channel data flow diagram.]]		[[File:Dig pic 44.png\|center\|Figure 2: 10 channel data flow diagram.]]

			=== [[Pipeline Structure]] ===
	The pipeline structure found in every channel is shown as Figure 3. The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image. When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.		The pipeline structure found in every channel is shown as Figure 3. The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image. When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.
	*Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.		*Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.

Copp at 16:31, October 18, 2021

2021-10-18T16:31:31Z

← Older revision		Revision as of 16:31, October 18, 2021
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	[[File:Dic pic 40.png\|center\|Figure 3: Pipeline structure of channel showing progression of waveform with time.]]		[[File:Dic pic 40.png\|center\|Figure 3: Pipeline structure of channel showing progression of waveform with time.]]

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Copp at 14:18, October 5, 2021

2021-10-05T14:18:42Z

← Older revision		Revision as of 14:18, October 5, 2021
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Copp at 16:49, September 29, 2021

2021-09-29T16:49:00Z

← Older revision		Revision as of 16:49, September 29, 2021
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	This section introduces mid-level descriptions for the topics of '''''Event Data Nomenclature''''', '''''Discriminator Modes''''', '''''Pileup Rejection''''', and '''''Diagnostic Counters'''''.		This section introduces mid-level descriptions for the topics of '''''Event Data Nomenclature''''', '''''Discriminator Modes''''', '''''Pileup Rejection''''', and '''''Diagnostic Counters'''''.

	The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer~~. Selective readout of events is achieved using an external trigger system~~. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit.		The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit.

	Each '''channel pipeline''' consists of a series of memory buffers used for delay. When sampling occurs, the timestamp value is saved. The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges~~. The discriminator implements a programmable hold-off time to ensure that the discriminator fires only once per edge. A discriminator firing captures timing and data sums simultaneously~~. Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth ([[IOC Code Design]])~~. No information reduction occurs in pileup conditions due to the fast discriminator recovery time~~.		Each '''channel pipeline''' consists of a series of memory buffers used for delay. When sampling occurs, the timestamp value is saved. The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges. Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth ([[IOC Code Design]]).

	All sampled values and sums are formatted into an '''event header''' that is followed by a programmable number of waveform samples. The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing.		All sampled values and sums are formatted into an '''event header''' that is followed by a programmable number of waveform samples. The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing.

	Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires. Programmable '''delay buffers''' positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. ~~When the discriminator fires these sums are saved and reported in the header.~~ These sums may then be used by ''open source user-maintained software'' (see the gitlab link in [[analysis codes]] for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header.		Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires. Programmable '''delay buffers''' positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. These sums may then be used by ''open source user-maintained software'' (see the gitlab link in [[analysis codes]] for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header.

	Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.		Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.

Copp at 16:46, September 29, 2021

2021-09-29T16:46:09Z

← Older revision		Revision as of 16:46, September 29, 2021
Line 17:		Line 17:
	This section introduces mid-level descriptions for the topics of '''''Event Data Nomenclature''''', '''''Discriminator Modes''''', '''''Pileup Rejection''''', and '''''Diagnostic Counters'''''.		This section introduces mid-level descriptions for the topics of '''''Event Data Nomenclature''''', '''''Discriminator Modes''''', '''''Pileup Rejection''''', and '''''Diagnostic Counters'''''.

	The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer. Selective readout of events is achieved using an external trigger system. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit. A down-sampling mode allows readout of averaged samples where each waveform sample in the readout may be the average of 2n ADC samples, from 2 to 128 (n = 0, 1, 2,…, 6, 7). Increased event rates are obtained by limiting the amount of waveform data read out per event.		The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer. Selective readout of events is achieved using an external trigger system. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit.

	Each '''channel pipeline''' consists of a series of memory buffers used for delay. ~~Discriminator logic recognizes edges within the input signal and causes data values to be sampled.~~ When sampling occurs, the timestamp value is saved. The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges. The discriminator implements a programmable hold-off time to ensure that the discriminator fires only once per edge. A discriminator firing captures timing and data sums simultaneously. ~~This data is buffered so that discriminator re-arms very quickly.~~ Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth ([[IOC Code Design]]). No information reduction occurs in pileup conditions due to the fast discriminator recovery time.		Each '''channel pipeline''' consists of a series of memory buffers used for delay. When sampling occurs, the timestamp value is saved. The discriminator logic may be configured as either leading-edge (slope) or constant-fraction architecture, sensitive to either positive-only, negative-only or both edges. The discriminator implements a programmable hold-off time to ensure that the discriminator fires only once per edge. A discriminator firing captures timing and data sums simultaneously. Firing rates over 1MHz can be supported, yet readout is limited to the IOCs total bandwidth ([[IOC Code Design]]). No information reduction occurs in pileup conditions due to the fast discriminator recovery time.

	All sampled values and sums are formatted into an '''event header''' that is followed by a programmable number of waveform samples. The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing. Flag bits provide useful diagnostics. The waveform data contains the raw ADC samples of the event, plus serialized timing mark bits that indicate when specific actions (discriminator, peak, timeouts, etc.) occurred and a 2nd bit that indicates whether samples are down-sampled (rescaled average of 2**n samples) or full-speed.		All sampled values and sums are formatted into an '''event header''' that is followed by a programmable number of waveform samples. The header contains various fields, including the timestamp of the event, the timestamp of the last time the discriminator of that channel fired, the timestamp of the peak, energy information, plus some energy/time information carried over from the previous discriminator firing.

	Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires. Programmable '''delay buffers''' positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. When the discriminator fires these sums are saved and reported in the header. These sums may then be used by ''open source user-maintained software'' (see the gitlab link in [[analysis codes]] for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header~~. This method is arithmetically identical to the traditional “trapezoid” method but is optimized for high rates of discriminator operation~~.		Energy measurement is performed in a double-correlated method timed relative to the moment the discriminator fires. Programmable '''delay buffers''' positioned to measure ranges of time before (pre-rise) and after (post-rise) the discriminator logic have accumulators continuously calculating the sum of all the ADC samples within them. When the discriminator fires these sums are saved and reported in the header. These sums may then be used by ''open source user-maintained software'' (see the gitlab link in [[analysis codes]] for GEBSort) to calculate the energy (amplitude) of the input signal, with all necessary baseline and pole-zero correction information obtained from the other information in the header.

	Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. ~~The reverse logic is also supported, in which only piled-up events are available for readout.~~ The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.		Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.

	== [[Digitizer Channel Design Overview]] ==		== [[Digitizer Channel Design Overview]] ==

Copp: /* Digitizer Channel Design Overview */

2021-09-29T16:37:53Z

Digitizer Channel Design Overview

← Older revision		Revision as of 16:37, September 29, 2021
Line 29:		Line 29:
	== [[Digitizer Channel Design Overview]] ==		== [[Digitizer Channel Design Overview]] ==
	This section covers mid-level descriptions of '''''Digitizer Channel Design''''', '''''Channel Interactions''''', and '''''Pipeline Structure'''''		This section covers mid-level descriptions of '''''Digitizer Channel Design''''', '''''Channel Interactions''''', and '''''Pipeline Structure'''''

			In the middle of the pipeline multiple delay buffers with accumulators provide running sums of the data spanning programmable ranges of time.

			[[File:Dig pic 44.png\|center\|Figure 2: 10 channel data flow diagram.]]

			The pipeline structure found in every channel is shown as Figure 3. The signal enters at the left and propagates to the right with time, backwards of a traditional oscilloscope image. When the edge of the signal reaches the middle, where the discriminator logic lies, the discriminator fires, capturing all the sum values shown plus timestamp and status information.
			*Note the discriminator in the middle of the design across buffer ‘d’, and the coarse discriminator placed well earlier in the pipeline.

			[[File:Dic pic 40.png\|center\|Figure 3: Pipeline structure of channel showing progression of waveform with time.]]


	''Go back to [[Digital Gammasphere and the SBX Upgrade]]''		''Go back to [[Digital Gammasphere and the SBX Upgrade]]''

Copp at 16:15, September 29, 2021

2021-09-29T16:15:47Z

← Older revision		Revision as of 16:15, September 29, 2021
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	== [[General Design of the Firmware]] ==		== [[General Design of the Firmware]] ==
	This section introduces mid-level descriptions for the topics of '''Event Data Nomenclature''', '''Discriminator Modes''', '''Pileup Rejection''', and '''Diagnostic Counters'''.		This section introduces mid-level descriptions for the topics of '''''Event Data Nomenclature''''', '''''Discriminator Modes''''', '''''Pileup Rejection''''', and '''''Diagnostic Counters'''''.

	The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer. Selective readout of events is achieved using an external trigger system. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit. A down-sampling mode allows readout of averaged samples where each waveform sample in the readout may be the average of 2n ADC samples, from 2 to 128 (n = 0, 1, 2,…, 6, 7). Increased event rates are obtained by limiting the amount of waveform data read out per event.		The ANL version of digitizer firmware implements ten independent data acquisition pipelines in ten channels. Pileup detection & rejection is performed locally within the digitizer. Selective readout of events is achieved using an external trigger system. Waveform readout of all events is possible, with up to 1024 ADC samples per channel per event, although this will limit the event rate as the VME backplane reaches its bandwidth limit. A down-sampling mode allows readout of averaged samples where each waveform sample in the readout may be the average of 2n ADC samples, from 2 to 128 (n = 0, 1, 2,…, 6, 7). Increased event rates are obtained by limiting the amount of waveform data read out per event.
Line 27:		Line 27:
	Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The reverse logic is also supported, in which only piled-up events are available for readout. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.		Hits captured by the discriminator may optionally be rejected if pileup occurs. If piled-up events are allowed the piling-on events may be read out in a variety of ways including extended and offset waveforms or just additional headers. The reverse logic is also supported, in which only piled-up events are available for readout. The firmware interfaces with an FPGA-based trigger system, also designed at ANL, to provide event selection based upon programmable trigger conditions. Specific triggering modes appropriate to the different detector systems at ANL have been developed.

	==~~= Event Data Nomenclature =~~==		== [[Digitizer Channel Design Overview]] ==
	~~Signal edges marked by discriminator firings are named~~ ''~~discriminator hits~~''.		This section covers mid-level descriptions of '''''Digitizer Channel Design''''', '''''Channel Interactions''''', and '''''Pipeline Structure'''''
	*''~~Discriminator hits~~'' ~~become accepted hits after passing through pileup rejection logic.~~
	*The firmware may run by itself (“internal accept all” mode) or with the trigger system (“TTCL mode”).
	~~# When running in “internal” mode~~ ''~~accepted hits~~'' ~~immediately become~~ ''~~accepted events~~'' ~~that are later read out.~~
	~~# When the trigger system is used~~ ''~~accepted hits~~'' wait in a queue for a limited time. The ''accepted hits'' in this queue only become ''accepted events'' if selected by a ''trigger accept message'' from the trigger. Accepted hits not marked as accepted events fall off the end of the pipeline and ~~are discarded.~~
	*The expectation is that all ''Accepted Events'' will be read out. ''Accepted Events'' ~~that were unable to be copied into the output buffer due to FIFO backup or other readout interference are named~~ '~~'dropped events''.~~
	~~# When using the trigger system, the digitizer may assert a~~ ''~~Throttle Request~~'' to the trigger if its FIFO is getting too full. This request, if honored, will result in the trigger suspending the issuance of trigger accept messages so that the readout system may drain the FIFO forming an automatic flow control mechanism to avoid ''~~dropped events~~''.

	~~==== Discriminator Modes ====~~
	The firmware supports either ''leading-edge'' or ''constant-fraction'' discriminator logic, independently selected per channel. In leading-edge mode the operation is controlled by a delay value ‘d’ and a threshold such that the discriminator fires if the difference between sample X(n) and sample X(n-d), after some filtering, is greater than the threshold. In constant-fraction mode, the user specifies a fraction value along with the same timing parameter ‘d’; the discriminator logic continuously calculates [X(n)*fraction] – X(d), and fires when this signal recrosses the initial value it had before the start of the edge.

	A 2nd, separate copy of the leading-edge discriminator, with its own threshold, called the coarse discriminator is also provided. The coarse discriminator fires well before the main discriminator does as it sees the edge earlier. The output of this device is used to capture early energy sum values well before the edge occurs, for use in pole-zero and/or baseline correction software after data is collected. Figure 3, later in this document, will explain these terms more fully.

	~~==== Pileup and Discriminator Hold-Off ====~~
	~~When pileup rejection is '''on''', ''discriminator hits'' become ''accepted hits'' only if there is no pileup.~~

	~~When pileup rejection is '''off''', discriminator hits always become accepted hits, but differentiation between the first accepted hit and all that pile up upon it (a “pileup train”) is needed~~

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