https://wiki.anl.gov/wiki_gsdaq/api.php?action=feedcontributions&feedformat=atom&user=Mcarpenter 2026-06-12T21:01:07Z User contributions MediaWiki 1.43.8 https://wiki.anl.gov/wiki_gsdaq/index.php?title=Main_Page&diff=2191 2021-09-16T15:30:01Z

<p>Mcarpenter: /* Experts Only */</p> <hr /> <div><br /> These are the wiki pages for the Digital and the analog Gammasphere Data Acquisition systems (GS DAQs). Procedures for running the DAQs and the data format will be documented here.<br /> <br /> The GS DAQ serves the Gammasphere detector array (http://www.phy.anl.gov/gammasphere/), located at the ATLAS accelerator (http://www.phy.anl.gov/atlas), home of the CAlifornium Rare Isotope Breeder Upgrade (CARIBU http://www.phy.anl.gov/atlas/caribu/).<br /> <br /> Contact mailto:torben@anl.gov for comments on, and write access to, these wiki pages<br /> <br /> ==Digital Gammasphere==<br /> <br /> o [[intro]]<br /> <br /> o [[typical DGS run procedures]]<br /> <br /> o [[receivers/GEBMerge/GEBsort]]<br /> <br /> o [[computers and networks]]<br /> <br /> o [[Raspberry Pi camera use]]<br /> <br /> o [[handeling removable disks under ESATA]]<br /> <br /> o [[triggers and digitizers]]<br /> <br /> o [[Digitizer Tester]]<br /> <br /> o [[The DGS/DFMA EPICS Implementation]]<br /> <br /> o [[data formats]]<br /> <br /> o [[analysis codes]]<br /> <br /> o [[list of experimental runs/analysis]]<br /> <br /> o [[some problems and their solutions]]<br /> <br /> o [[hint and kinks]]<br /> <br /> o [[firmware documentation]]<br /> <br /> o [[Tim Madden software documentation]]<br /> <br /> ==Analog Gammasphere==<br /> <br /> o [[Analog Gammasphere]]<br /> <br /> o [[LN system]]<br /> <br /> o [[JohnSandbox]]<br /> <br /> ==Experts Only==<br /> <br /> o [[Building the entire system]]<br /> <br /> o [[Linking Systems Together]]<br /> <br /> o [[Updating Firmware in Digitizers and Triggers]]<br /> <br /> ==Hardware==<br /> <br /> * [[Network Accessible Power Control Units of DGS]]<br /> * [[Attempts at Inventory]]<br /> * [https://wiki.anl.gov/wiki_gsdaq/images/4/40/MyRIAD_User_Manaual.pdf MyRIAD_User_Manaual]<br /> * [https://wiki.anl.gov/wiki_gsdaq/images/1/16/MyRIAD_Abridged_User_Notes.pdf MyRIAD_Abridged_User_Notes]<br /> * [[CrateAndBoardMapping]]<br /> <br /> ===Digitizer hardware features you probably don't know about===<br /> <br /> * The digitizer has a [[DAC output]].<br /> * The digitizer has a buffer amplifier that drives a copy of the analog signal going into channel 9 to outputs on the front panel. This is a simple analog buffer, no shaping, sampling or anything else.<br /> *<br /> <br /> ==contact list==<br /> <br /> Mike Carpenter, mailto:carpenter@anl.gov<br /> <br /> John Anderson, mailto:jta@anl.gov<br /> <br /> Michael Oberling, mailto:moberling@anl.gov<br /> <br /> Torben Lauritsen, mailto:torben@anl.gov<br /> <br /> Darek Seweryniak, mailto:seweryniak@anl.gov<br /> <br /> Pat Copp, mailto:copp@anl.gov<br /> <br /> Amel Korichi, mailto:korichi@csnsm.in2p3.fr<br /> <br /> <br /> {{Template:Standard Footer}}</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2190 2021-09-16T13:55:46Z

<p>Mcarpenter: </p> <hr /> <div>==Some more notes about flashing digitizers or triggers:==<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as: epics.sendFgga(Firmwarename, ret file name, Crate num, Board num, erase, program, verify)<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> ==Below are cut and paste commands to use with DGS or DFMA ==<br /> === Trigger and Routers ===<br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> ===DGS Digitizers===<br /> '''master digitzers'''&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> '''slave digitzers'''&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> ===For Non-Slave Configuration (FMA):===<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2189 2021-09-16T13:54:43Z

<p>Mcarpenter: </p> <hr /> <div>==Some more notes about flashing digitizers or triggers:==<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as: epics.sendFgga(Firmwarename, ret file name, Crate num, Board num, erase, program, verify)<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> ==Below are cut and paste commands to use with DGS or DFMA ==<br /> === Trigger and Routers ===<br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> ===DGS Digitizers===&lt;br/&gt;<br /> '''master digitzers'''&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> '''slave digitzers'''&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> ===For Non-Slave Configuration (FMA):===<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2188 2021-09-16T13:52:39Z

<p>Mcarpenter: </p> <hr /> <div>==Some more notes about flashing digitizers or triggers:==<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as: epics.sendFgga(Firmwarename, ret file name, Crate num, Board num, erase, program, verify)<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> ==Below are cut and paste commands to use with DGS or DFMA ==<br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2187 2021-09-16T13:51:21Z

<p>Mcarpenter: </p> <hr /> <div>==Some more notes about flashing digitizers or triggers:==<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as: epics.sendFgga(Firmwarename, ret file name, Crate num, Board num, erase, program, verify)<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Below are cut and paste commands to use with DGS or DFMA ===<br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2186 2021-09-16T13:49:44Z

<p>Mcarpenter: </p> <hr /> <div>==Some more notes about flashing digitizers or triggers:==<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Below are cut and paste commands to use with DGS or DFMA ===<br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2185 2021-09-16T13:48:35Z

<p>Mcarpenter: </p> <hr /> <div>==Some more notes about flashing digitizers or triggers:==<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Below are cut and paste commands to use with DGS or DFMA ===<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2184 2021-09-16T13:47:43Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ## We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ## You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Below are cut and paste commands to use with DGS or DFMA ===<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2183 2021-09-16T13:46:59Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get the *.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> ** We have 4 flavors, MSTR_digitizer, SLAVE_digitizer, trigger_top and router_top<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> ** You can rename file to reflect the date compiled e.g. MSTR_digitizer_2020722.bin<br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Below are cut and paste commands to use with DGS or DFMA ===<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2182 2021-09-16T05:39:21Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Below are cut and paste commands to use with DGS or DFMA ===<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2181 2021-09-16T05:38:26Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> === Heading text ===<br /> Below are cut and paste commands to use with DGS or DFMA<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2180 2021-09-16T05:36:49Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed but power cycle also works for digitizers too. &lt;br/&gt;<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2179 2021-09-15T21:05:24Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> <br /> '''master digitzers'''&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);&lt;br/&gt;<br /> <br /> '''For Non-Slave Configuration (FMA):'''&lt;br/&gt;<br /> &lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);&lt;br/&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2178 2021-09-15T21:00:20Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> '''DGS Digitizers'''&lt;br/&gt;<br /> <br /> <br /> '''master digitzers'''<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);&lt;br/&gt;<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);&lt;br/&gt;<br /> <br /> <br /> '''slave digitzers'''&lt;br/&gt;<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);<br /> <br /> <br /> For Non-Slave Configuration (FMA):<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> <br /> Not sure if VME10 is crate 9 or 10<br /> <br /> Gammasphere<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 3, 1,1,1);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2177 2021-09-15T18:54:03Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.<br /> <br /> '''For master trigger'''&lt;br/&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br/&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> '''add these for FMA'''&lt;br/&gt;<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);&lt;br/&gt;<br /> <br /> DGS Digitizers&lt;br/&gt;<br /> <br /> <br /> master digitzers<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);<br /> <br /> <br /> slave digitzers<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);<br /> <br /> <br /> For Non-Slave Configuration (FMA):<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> <br /> Not sure if VME10 is crate 9 or 10<br /> <br /> Gammasphere<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 3, 1,1,1);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2176 2021-09-15T18:52:23Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.<br /> <br /> '''For master trigger'''&lt;br\&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br\&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br\&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br\&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br\&gt;<br /> <br /> '''add these for FMA'''<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);<br /> <br /> DGS Digitizers<br /> <br /> <br /> master digitzers<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);<br /> <br /> <br /> slave digitzers<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);<br /> <br /> <br /> For Non-Slave Configuration (FMA):<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> <br /> Not sure if VME10 is crate 9 or 10<br /> <br /> Gammasphere<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 3, 1,1,1);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2175 2021-09-15T15:38:46Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.<br /> <br /> '''For master trigger'''&lt;br\&gt;<br /> epics.sendFpga(mastware, fn1, 0, 0,1, 1, 1);&lt;br\&gt;<br /> <br /> '''For routers'''&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 1,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 2,1, 1, 1);&lt;br/&gt;<br /> epics.sendFpga(routware, fn1, 0, 3,1, 1, 1);&lt;br/&gt;<br /> <br /> add these for FMA<br /> <br /> epics.sendFpga(routware, fn1, 0, 4,1, 1, 1);<br /> epics.sendFpga(routware, fn1, 0, 5,1, 1, 1);<br /> <br /> DGS Digitizers<br /> <br /> <br /> master digitzers<br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,0);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,0);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,0);<br /> <br /> <br /> slave digitzers<br /> <br /> epics.sendFpga(slvware, fn1, 1, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 1, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 2, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 3, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 4, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 5, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 6, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 7, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 8, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 9, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 10, 3, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 1, 1,1,0);<br /> <br /> epics.sendFpga(slvware, fn1, 11, 3, 1,1,0);<br /> <br /> <br /> For Non-Slave Configuration (FMA):<br /> <br /> epics.sendFpga(digware, fn1, 1, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 1, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 2, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 3, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 4, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 5, 3, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 0, 1,1,1);<br /> <br /> epics.sendFpga(digware, fn1, 6, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 6, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 7, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 8, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> <br /> Not sure if VME10 is crate 9 or 10<br /> <br /> Gammasphere<br /> epics.sendFpga(digware, fn1, 9, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 9, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 10, 3, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 0, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 1, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 2, 1,1,1);<br /> epics.sendFpga(digware, fn1, 11, 3, 1,1,1);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2174 2021-09-15T15:28:15Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> * To Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. <br /> * To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. <br /> * For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2173 2021-09-15T15:25:35Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;<br /> <br /> If you get this far, you are now ready to flash the individual digitizers<br /> <br /> * To flash digitizer type epics.sendFpga(digware, fn1, 1, 0,1, 1, 1);<br /> ** This line sends the firmware file defined in digware to the board.<br /> ** The args of the function are defined as:   <br /> *** Firmwarename, ret file name, Crate num, Board num, erase, program, verify<br /> ** IN the above function, we send digware to crate 1, board 0 and erase, program and verify the fpga.<br /> <br /> - Update the FPGA so it runs the new firmware. ON the dig boards there is a PV called GLBL:DIG:config_main_fpga that will reconfigure ALL digitizer FPGAs in DGS. This is convenient. To update a single FPGA, say in VME1, we use VME01:DIG1:config_main_fpga. Simple write a 1 to these PVs to reconfig the FPGAs. For the Trigger crate, a power cycle is needed. CSS screens have controls for these PVs. The easiest is on the Global Control screen accessible from the main DGSCommander screen. Simply hit the button for config main fpga to reconfigure ALL digitizer FPGAs. Trigger FPGAs are not affected.</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2172 2021-09-15T15:19:25Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> -'''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names''' &lt;br&gt;<br /> -'''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.''' &lt;br&gt;<br /> -'''NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''&lt;br&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2171 2021-09-15T15:18:03Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> '''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names'''<br /> - '''NOTE: If bin file name is wrong, program will still try to flash and result will be yellow fever.<br /> - NOTE: The asynRecords.txt file defines the active crates. If you get a missing PV during setup, edit this file or better yet, make a new one and assign it instead.'''</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2170 2021-09-15T15:14:59Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> '''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names'''</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2169 2021-09-15T15:14:29Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> '''NOTE: Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names'''</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2168 2021-09-15T15:14:00Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # issue following: java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;<br /> <br /> NOTEL Need to define add current name of master, slave digitizer bin files and trigger &amp; router bin file names</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2167 2021-09-15T15:11:05Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> epics.epics_init(); &lt;br&gt;<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;); &lt;br&gt;<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;); &lt;br&gt;<br /> epics.connectPVs(fn0); &lt;br&gt;<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;); &lt;br&gt;<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);&lt;br&gt;<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);&lt;br&gt;<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);&lt;br&gt;</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2166 2021-09-15T15:09:37Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl &lt;br&gt;<br /> epics.epics_init();<br /> <br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;);<br /> <br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;);<br /> <br /> epics.connectPVs(fn0);<br /> <br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;);<br /> <br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);<br /> <br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);<br /> <br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2165 2021-09-15T15:06:34Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl<br /> epics.epics_init();<br /> <br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;);<br /> <br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;);<br /> <br /> epics.connectPVs(fn0);<br /> <br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;);<br /> <br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);<br /> <br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);<br /> <br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2164 2021-09-15T15:06:09Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl<br /> <br /> epics.epics_init();<br /> <br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;);<br /> <br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;);<br /> <br /> epics.connectPVs(fn0);<br /> <br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;);<br /> <br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);<br /> <br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);<br /> <br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2163 2021-09-15T15:05:13Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src<br /> # copy and paste below<br /> <br /> java -classpath jca-2.3.5.jar:caj-1.1.9.jar:fpgasender.jar plotControl<br /> epics.epics_init();<br /> var fn0=new String(&quot;/home/dgs/tmadden/swWork/workspace/epicsClient/src/asynRecords.txt&quot;);<br /> var fn1=new String(&quot;/home/dgs/tmadden/retfile.bin&quot;);<br /> epics.connectPVs(fn0);<br /> var digware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/MSTR_digitizer_20200722.bin&quot;);<br /> var slvware=new String(&quot;/home/dgs/tmadden/DGSDigFirmware/SLAVE_digitizer_20200602.bin&quot;);<br /> var mastware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/trigger_top_20160626.bin&quot;);<br /> var routware=new String(&quot;/home/dgs/tmadden/DGSTrigFirmware/router_top_20160601.bin&quot;);</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2162 2021-09-15T15:00:25Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from directory /Digitizer/MAIN_FPGA/Work11_DGS<br /> # copy to /home/dgs/tmadden/DGSDigFirmware or /home/dgs/tmadden/DGSTrigFirmware <br /> # cd /home/dgs/tmadden/swWork/workspace/epicsClient/src</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2161 2021-09-15T14:56:14Z

<p>Mcarpenter: </p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> # Get digitizer.bin from svn and copy it to directory /Digitizer/MAIN_FPGA/Work11_DGS</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Updating_Firmware_in_Modules&diff=2160 2021-09-15T14:55:42Z

<p>Mcarpenter: Created page with &quot;Some more notes about flashing digitizers or triggers: # Log into dgs account on dgs1 Get digitizer.bin from svn and copy it to directory /Digitizer/MAIN_FPGA/Work11_DGS&quot;</p> <hr /> <div>Some more notes about flashing digitizers or triggers:<br /> # Log into dgs account on dgs1<br /> Get digitizer.bin from svn and copy it to directory /Digitizer/MAIN_FPGA/Work11_DGS</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Main_Page&diff=2159 2021-09-15T14:48:33Z

<p>Mcarpenter: /* Experts Only */</p> <hr /> <div><br /> These are the wiki pages for the Digital and the analog Gammasphere Data Acquisition systems (GS DAQs). Procedures for running the DAQs and the data format will be documented here.<br /> <br /> The GS DAQ serves the Gammasphere detector array (http://www.phy.anl.gov/gammasphere/), located at the ATLAS accelerator (http://www.phy.anl.gov/atlas), home of the CAlifornium Rare Isotope Breeder Upgrade (CARIBU http://www.phy.anl.gov/atlas/caribu/).<br /> <br /> Contact mailto:torben@anl.gov for comments on, and write access to, these wiki pages<br /> <br /> ==Digital Gammasphere==<br /> <br /> o [[intro]]<br /> <br /> o [[typical DGS run procedures]]<br /> <br /> o [[receivers/GEBMerge/GEBsort]]<br /> <br /> o [[computers and networks]]<br /> <br /> o [[Raspberry Pi camera use]]<br /> <br /> o [[handeling removable disks under ESATA]]<br /> <br /> o [[triggers and digitizers]]<br /> <br /> o [[Digitizer Tester]]<br /> <br /> o [[The DGS/DFMA EPICS Implementation]]<br /> <br /> o [[data formats]]<br /> <br /> o [[analysis codes]]<br /> <br /> o [[list of experimental runs/analysis]]<br /> <br /> o [[some problems and their solutions]]<br /> <br /> o [[hint and kinks]]<br /> <br /> o [[firmware documentation]]<br /> <br /> o [[Tim Madden software documentation]]<br /> <br /> ==Analog Gammasphere==<br /> <br /> o [[Analog Gammasphere]]<br /> <br /> o [[LN system]]<br /> <br /> o [[JohnSandbox]]<br /> <br /> ==Experts Only==<br /> <br /> o [[Building the entire system]]<br /> <br /> o [[Linking Systems Together]]<br /> <br /> o [[Updating Firmware in Modules]]<br /> <br /> ==Hardware==<br /> <br /> * [[Network Accessible Power Control Units of DGS]]<br /> * [[Attempts at Inventory]]<br /> * [https://wiki.anl.gov/wiki_gsdaq/images/4/40/MyRIAD_User_Manaual.pdf MyRIAD_User_Manaual]<br /> * [https://wiki.anl.gov/wiki_gsdaq/images/1/16/MyRIAD_Abridged_User_Notes.pdf MyRIAD_Abridged_User_Notes]<br /> * [[CrateAndBoardMapping]]<br /> <br /> ===Digitizer hardware features you probably don't know about===<br /> <br /> * The digitizer has a [[DAC output]].<br /> * The digitizer has a buffer amplifier that drives a copy of the analog signal going into channel 9 to outputs on the front panel. This is a simple analog buffer, no shaping, sampling or anything else.<br /> *<br /> <br /> ==contact list==<br /> <br /> Mike Carpenter, mailto:carpenter@anl.gov<br /> <br /> John Anderson, mailto:jta@anl.gov<br /> <br /> Michael Oberling, mailto:moberling@anl.gov<br /> <br /> Torben Lauritsen, mailto:torben@anl.gov<br /> <br /> Darek Seweryniak, mailto:seweryniak@anl.gov<br /> <br /> Pat Copp, mailto:copp@anl.gov<br /> <br /> Amel Korichi, mailto:korichi@csnsm.in2p3.fr<br /> <br /> <br /> {{Template:Standard Footer}}</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Run_procedures&diff=1787 2013-01-28T22:45:30Z

<p>Mcarpenter: </p> <hr /> <div>==start DAQ==<br /> <br /> There are 3 controls associated with Run Control on the main page of either GUI<br /> <br /> * Start/Stop - this is self explanatory. Pushing to start begins taking data.<br /> * NoSave/Save - If set to Save, IOC buffers fill with data. You must attach a receiver to each digitizer IOC or the system may crash horribly once the buffers fill up.<br /> * Copy/Sort - In Sort mode, the data out of the IOC is time ordered according to the time stamp.<br /> <br /> Good instructions makes things easy, that is why we have none. <br /> <br /> ==stop DAQ==<br /> write your instructions here<br /> <br /> ==Changing gain in Phill's signal box== <br /> write your instructions here<br /> <br /> ==Linking two or more systems==<br /> <br /> write your instructions here<br /> <br /> ==syncing two systems==<br /> <br /> For DGS<br /> <br /> * Goto trig0 window.<br /> * Turn off SYNC U - listed under LRU Control<br /> * Make sure receive/send power is on for L &amp; U<br /> <br /> '''Note:''' If SYNC U is turned off - an Impeartive sync by DGS will reset the master clock on DFMA.<br /> <br /> For DFMA<br /> <br /> * Goto Trig0 Window<br /> * Under Misc Control - turn on both undefined buttons<br /> * Pull up diagnotsitc window on trig0.<br /> * Set Clrk Source to LINK<br /> * Set Nim1 and Nim2 out on master trigger module FMA<br /> <br /> '''Note:''' Clock Source cannot be set to LINK in GUI. Set address 0x8D0 in slot 0 to set 1 for trigger modules. This needs to be fixed in Driver by Tim.<br /> <br /> ==receivers==<br /> <br /> write your instructions here<br /> <br /> ==cables==<br /> <br /> write your instructions here<br /> <br /> ==changing FPGA Firmware code==<br /> <br /> write your instructions here</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Run_procedures&diff=1748 2013-01-04T22:05:19Z

<p>Mcarpenter: /* syncing two systems */</p> <hr /> <div>==start DAQ==<br /> <br /> this is how you start the daq,<br /> <br /> * first you do this<br /> * then you do that<br /> * and then it crashes<br /> * and then you call Mike<br /> <br /> Good instructions makes things easy, that is why we have none. <br /> <br /> <br /> ==stop DAQ==<br /> write your instructions here<br /> <br /> ==gtsort==<br /> <br /> write your instructions here<br /> ==linking two or more systems==<br /> <br /> write your instructions here<br /> <br /> ==syncing two systems==<br /> <br /> For DGS<br /> <br /> * Goto trig0 window.<br /> * Turn off SYNC U - listed under LRU Control<br /> * Make sure receive/send power is on for L &amp; U<br /> <br /> '''Note:''' If SYNC U is turned off - an Impeartive sync by DGS will reset the master clock on DFMA.<br /> <br /> For DFMA<br /> <br /> * Goto Trig0 Window<br /> * Under Misc Control - turn on both undefined buttons<br /> * Pull up diagnotsitc window on trig0.<br /> * Set Clrk Source to LINK<br /> * Set Nim1 and Nim2 out on master trigger module FMA<br /> <br /> '''Note:''' Clock Source cannot be set to LINK in GUI. Set address 0x8D0 in slot 0 to set 1 for trigger modules. This needs to be fixed in Driver by Tim.<br /> <br /> ==receivers==<br /> <br /> write your instructions here<br /> <br /> ==cables==<br /> <br /> write your instructions here<br /> <br /> ==changing FPGA code==<br /> <br /> <br /> write your instructions here</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Run_procedures&diff=1747 2013-01-04T22:04:30Z

<p>Mcarpenter: /* syncing two systems */</p> <hr /> <div>==start DAQ==<br /> <br /> this is how you start the daq,<br /> <br /> * first you do this<br /> * then you do that<br /> * and then it crashes<br /> * and then you call Mike<br /> <br /> Good instructions makes things easy, that is why we have none. <br /> <br /> <br /> ==stop DAQ==<br /> write your instructions here<br /> <br /> ==gtsort==<br /> <br /> write your instructions here<br /> ==linking two or more systems==<br /> <br /> write your instructions here<br /> <br /> ==syncing two systems==<br /> <br /> For DGS<br /> <br /> * Goto trig0 window.<br /> * Turn off SYNC U - listed under LRU Control<br /> * Make sure receive/send power is on for L &amp; U<br /> <br /> '''Note:''' If SYNC U is turned off - an Implicit sync by DGS will reset the master clock on DFMA.<br /> <br /> For DFMA<br /> <br /> * Goto Trig0 Window<br /> * Under Misc Control - turn on both undefined buttons<br /> * Pull up diagnotsitc window on trig0.<br /> * Set Clrk Source to LINK<br /> * Set Nim1 and Nim2 out on master trigger module FMA<br /> <br /> '''Note:''' Clock Source cannot be set to LINK in GUI. Set address 0x8D0 in slot 0 to set 1 for trigger modules. This needs to be fixed in Driver by Tim.<br /> <br /> ==receivers==<br /> <br /> write your instructions here<br /> <br /> ==cables==<br /> <br /> write your instructions here<br /> <br /> ==changing FPGA code==<br /> <br /> <br /> write your instructions here</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Run_procedures&diff=1746 2013-01-04T22:03:56Z

<p>Mcarpenter: /* syncing two systems */</p> <hr /> <div>==start DAQ==<br /> <br /> this is how you start the daq,<br /> <br /> * first you do this<br /> * then you do that<br /> * and then it crashes<br /> * and then you call Mike<br /> <br /> Good instructions makes things easy, that is why we have none. <br /> <br /> <br /> ==stop DAQ==<br /> write your instructions here<br /> <br /> ==gtsort==<br /> <br /> write your instructions here<br /> ==linking two or more systems==<br /> <br /> write your instructions here<br /> <br /> ==syncing two systems==<br /> <br /> For DGS<br /> <br /> * Goto trig0 window.<br /> * Turn off SYNC U - listed under LRU Control<br /> * Make sure receive/send power is on for L &amp; U<br /> <br /> '''Note:''' If SYNC U is turned off - an Implicit sync by DGS will reset the master clock on DFMA.<br /> <br /> For DFMA<br /> <br /> * Goto Trig0 Window<br /> * Under Misc Control - turn on both undefined buttons<br /> * Pull up diagnotsitc window on trig0.<br /> * Set Clrk Source to LINK<br /> * Set Nim1 and Nim2 out on master trigger module FMA<br /> <br /> '''Note:''' Clock Source cannot be set to LINK in GUI. Set address 0x8D0 in slot 0 to set 1 for trigger modules. This needs to be fixed<br /> <br /> ==receivers==<br /> <br /> write your instructions here<br /> <br /> ==cables==<br /> <br /> write your instructions here<br /> <br /> ==changing FPGA code==<br /> <br /> <br /> write your instructions here</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Run_procedures&diff=1745 2013-01-04T22:02:44Z

<p>Mcarpenter: /* syncing two systems */</p> <hr /> <div>==start DAQ==<br /> <br /> this is how you start the daq,<br /> <br /> * first you do this<br /> * then you do that<br /> * and then it crashes<br /> * and then you call Mike<br /> <br /> Good instructions makes things easy, that is why we have none. <br /> <br /> <br /> ==stop DAQ==<br /> write your instructions here<br /> <br /> ==gtsort==<br /> <br /> write your instructions here<br /> ==linking two or more systems==<br /> <br /> write your instructions here<br /> <br /> ==syncing two systems==<br /> <br /> For DGS<br /> <br /> * Goto trig0 window.<br /> * Turn off SYNC U - listed under LRU Control<br /> * Make sure receive/send power is on for L &amp; U<br /> <br /> '''Note:''' If SYNC U is turned off - an Implicit sync by DGS will reset the master clock on DFMA.<br /> <br /> For DFMA<br /> <br /> * Goto Trig0 Window<br /> * Under Misc Control - turn on both undefined buttons<br /> * Pull up diagnotsitc window on trig0.<br /> * Set Clrk Source to LINK<br /> * Set Nim1 and Nim2 out on master trigger module FMA<br /> <br /> '''Note:''' Clock Source does not set to link. Set address 0x8D0 in slot 0 to set 1 for trigger modules. This needs to be fixed<br /> <br /> ==receivers==<br /> <br /> write your instructions here<br /> <br /> ==cables==<br /> <br /> write your instructions here<br /> <br /> ==changing FPGA code==<br /> <br /> <br /> write your instructions here</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Run_procedures&diff=1744 2013-01-04T22:00:52Z

<p>Mcarpenter: /* syncing two systems */</p> <hr /> <div>==start DAQ==<br /> <br /> this is how you start the daq,<br /> <br /> * first you do this<br /> * then you do that<br /> * and then it crashes<br /> * and then you call Mike<br /> <br /> Good instructions makes things easy, that is why we have none. <br /> <br /> <br /> ==stop DAQ==<br /> write your instructions here<br /> <br /> ==gtsort==<br /> <br /> write your instructions here<br /> ==linking two or more systems==<br /> <br /> write your instructions here<br /> <br /> ==syncing two systems==<br /> <br /> For DGS<br /> <br /> * Goto trig0 window.<br /> * Turn off SYNC U - listed under LRU Control<br /> * Make sure receive/send power is on for L &amp; U<br /> <br /> '''Note:''' If SYNC U is turned off - an Implicit sync by DGS will reset the master clock on DFMA.<br /> <br /> For DFMA<br /> <br /> * Goto Trig0 Window<br /> * Under Misc Control - turn on both undefined buttons<br /> * Pull up diagnotsitc window on trig0.<br /> * Set Clrk Source to LINK<br /> * Set Nim1 and Nim2 out on master trigger module FMA<br /> <br /> '''Note:''' Clock Source does not set to link. Set address 0x8D0 in slot 0 to set 1 for trigger modules. This needs to be fixed<br /> <br /> ==receivers==<br /> <br /> write your instructions here<br /> <br /> ==cables==<br /> <br /> write your instructions here<br /> <br /> ==changing FPGA code==<br /> <br /> <br /> write your instructions here</div>

Mcarpenter https://wiki.anl.gov/wiki_gsdaq/index.php?title=Main_Page&diff=1743 2013-01-04T21:56:42Z

<p>Mcarpenter: </p> <hr /> <div><br /> These are the wiki pages for the Digital Gammasphere Data Acquisition system (GS DAQ). Procedures for running the DAQ and the data format will be documented here.<br /> <br /> The GS DAQ serves the Gammasphere detector array (http://www.phy.anl.gov/gammasphere/), located at the ATLAS accelerator (http://www.phy.anl.gov/atlas), home of the CAlifornium Rare Isotope Breeder Upgrade (CARIBU http://www.phy.anl.gov/atlas/caribu/).<br /> <br /> Contact mailto:torben@anl.gov for comments on these wiki pages<br /> <br /> <br /> o [[intro]]<br /> <br /> o [[computers and networks]]<br /> <br /> o [[run procedures]]<br /> <br /> o [[data formats]]<br /> <br /> o [[analysis codes]]<br /> <br /> o [[list of experimental runs/analysis]]<br /> <br /> o [[some problems and their solutions]]<br /> <br /> ==contact list==<br /> <br /> Mike Carpenter, mailto:carpenter@anl.gov<br /> <br /> John Anderson, mailto:<br /> <br /> Tim Madden, mailto:<br /> <br /> Michael Oberling, mailto:<br /> <br /> Shaofei Zhu, mailto:<br /> <br /> Torben Lauritsen, mailto:torben@anl.gov<br /> <br /> <br /> etc<br /> <br /> <br /> <br /> {{Template:Standard Footer}}</div>

Mcarpenter